Modeling and Evaluation of Multi-Bank SRAM Design for Leakage Power Reduction
نویسندگان
چکیده
In this paper, the modeling and evaluation of multibank SRAM design with dynamic threshold and supply voltage control is presented to reduce leakage power. The bank of SRAM, the unit of control, is put in sleep mode (high threshold voltage and low supply voltage) from active mode (low threshold voltage and high supply voltage) whenever it is not frequently used. The change of modes is based on the characteristics of the temporal and spatial locality of memory accesses. The simulation results show that significant leakage reduction can be achieved through combined implementation of spatial locality and temporal locality while minimizing the re-synchronization penalties when the size of superbank is optimized based on the characteristics of application program.
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